This invention relates to apparatus and techniques for regulating voltages. More specifically, this invention relates to apparatus and techniques using multi-channel, multi-phase regulatorsxe2x80x94i.e., regulators that use multiple small regulators with interleaved phases, wherein each small regulator represents a channel, to produce a single regulated output.
The evolution of logic and computing devices has resulted in a need for smaller loadpoint power regulators to supply lower voltages and higher currents. High efficiency at full load is essential for alleviating the thermal stress that results from increased heat generated by higher current in a smaller space. PWM switched mode power conversion techniques and low ON-resistance MOSFETs are usually adopted for these types of high current applications in order to minimize the conduction loss at full load conditions. However, low ON-resistance MOSFETs tend to have large parasitic capacitance and gate charge, which may cause high switching losses and gate-drive losses at high switching frequencies.
Because high switching frequencies introduce significant switching related power loss in semiconductors and core loss in magnetic components, it follows that decreasing the effective switching frequency at light loads reduces the switching related loss and increases the efficiency. Although the conduction loss drops significantly at light loads because it is proportional to the square of the current, an unnecessarily large number of MOSFETs are still switched, resulting in excessive switching loss and gate driving loss.
In fact, under light load conditions, switching-related power losses dominate. The efficiency at light loads suffers greatly. This conflicts with the widely adopted Energy Star requirement, which demands that efficiency at light loads be maximized when the system is in stand-by mode.
This problem can be at least partially alleviated by employing the multi-phase or PolyPhase(copyright) PWM technique. This technique is more fully described in co-pending, commonly assigned U.S. patent application Ser. No. 09/114,384, filed Jul. 13, 1998, which is incorporated by reference herein in its entirety. Instead of using a single bulky power regulator, which relies on increasing the frequency to reduce the size of power supply, the PolyPhase technique parallels several small regulators and interleaves the phases of their clock signals. Utilizing small regulators reduces the size of the capacitors and inductors required by the circuit. This is made possible, at least in part, by input and output ripple current cancellation between the multiple regulators which occurs when the phases are properly interleaved. Because the switching frequency for each individual regulator remains relatively low, the switching losses associated with the individual power MOSFETs are smaller. This helps maintain a relatively high efficiency at light load.
It would be desirable to further increase the light load efficiency in a multi-channel multi-phase regulator.
It is an object of the invention to further increase the light load efficiency in a multi-channel multi-phase regulator.
A multi-channel multi-phase voltage regulator that has an output is provided. The regulator includes at least one detection circuit that compares the output to a threshold value and shuts down at least one channel of the multi-channel multi-phase regulator when the detection circuit determines that, based on the comparison, the output is in a light load condition.
In an alternative embodiment of the invention, the detection circuit may also place remaining channels that were not shut down in stand-by mode when the output is determined to be in a light load condition.